That also makes for some very interesting timings, where the instruction runs faster in the case that there's no carry between the two halves.

From section 2 of this:

https://gmplib.org/~tege/x86-timing.pdf

"Pentium F0-F2 can sustain 3 add r, i per cycle for -32768 <= i <= 32767, but for larger immediate operands it can sustain only about 3/2 per cycle."