The ALU performs an operation on half of the machine word (16 of the 32 bits) each half-cycle, i.e., one on the rising edge and one on the falling edge of the clock. Basically they split the carry chain across two (half-)pipe stages and then run it twice as fast.

See Hinton et al., "The microarchitecture of the Pentium 4 processor" [1] for all the nifty details -- pp 8-9, and Fig 7 in particular.

[1] http://www.ecs.umass.edu/ece/koren/ece568/papers/Pentium4.pd...

That also makes for some very interesting timings, where the instruction runs faster in the case that there's no carry between the two halves.

From section 2 of this:

https://gmplib.org/~tege/x86-timing.pdf

"Pentium F0-F2 can sustain 3 add r, i per cycle for -32768 <= i <= 32767, but for larger immediate operands it can sustain only about 3/2 per cycle."

Makes sense, thanks!

It runs at 2x the clock rate as the main chip. So if the chip is running at 2Ghz, the ALU is running at 4Ghz.

While this might not make sense at the surface (the next stage of the pipeline won't be ready for the data a half clock cycle earlier), you can minimize logic area by doing 2 quick 16 bit operations. Additionally, for some operations that have dependent instructions, for example a super scalar processor executing two integer instructions at once, if you have an ADD that depends on another ADD, you can forward the result from the first cycle on the first ALU to the second cycle on the second, although I'm not sure if this is actually done.

Another case where this is useful is if the result of an ADD operation needs to be used on a LOAD instruction earlier, you can forward the result a half clock cycle sooner.