Process metrics are somewhat of a marketing nature nowadays (and not as directly related to the physical properties of the fabrication process as it may seem--at least not without adjusting for the differences between vendor-specific definitions in use).
Compare TSMC's 10nm to Intel's 14nm:
"In the case of TSMC they follow the “Foundry” node progress whereas Intel follows more of an “IDM” node transition 40nm versus 45nm, 28nm versus 32nm and 20nm versus 22nm. At the 14nm node TSMC has also chosen to call their node 16nm where everyone else is calling it 14nm."
Source: https://www.semiwiki.com/forum/content/3884-who-will-lead-10...
"Although the nominal gap in process nodes between Intel and TSMC appears to be narrowing, TSMC is not likely to catch up in terms of actual Moore’s Law scaling any time soon. TSMC’s 16FF+ process delivers only 20nm scaling, so they are still a generation behind Intel’s 14nm in terms of actual die area. TSMC said that 10nm shrinks by 0.52x from 16nm, nearly identical to the 0.53x scaling that Intel achieved from 22nm to 14nm. So if they stay on schedule, in 2017 TSMC will be in production on a 10nm process that is equivalent to the 14nm technology that Intel began producing in 2Q15. At that rate, even though Intel has slipped 10nm to 2H17, they will remain at least a year ahead of TSMC."
These numbers refer to the length of the channel in the MOSFET or FinFET between the Source and Drain dopant regions. The channel is always the smallest feature the fabrication process can create, but how it's created is actually with lots of solid-state physics tricks (such as annealing to cause the dopants to spread out from where they were originally implanted, looking a lot like a physical Gaussian blur), as the original masks used to define the transistor are nowhere near that small.
Depending on how small they can get the mask details (mostly an issue of optics and mask creation, now bounded primarily by the frequency of light they expose to the mask material, though interesting holographic tricks can help if they've left the laboratory phase) you can define the minimum size of the transistors, themselves. But there are other considerations like heat dissipation and the melting points of the various metals you've used that may force the transistors to be larger than what you can theoretically build.
The channel length is still very important because it determines how many Coulombs of charge you need to switch the transistor on, and how long it takes to propagate a signal across the transistor.
It also correlates with how much leakage current the transistor has (smaller = higher) and therefore the standby power consumption, so you do continue to make an engineering trade-off to get lower, which is also why server hardware tends to get the smallest sizes first, as they least care about idle power consumption if they're being utilized correctly.
Everything I've said is about 4 years out of date, when I switched from EE back to Software Engineering for financial reasons (and also my wife is an EE so we didn't want to put all of our financial eggs in one basket), but the semiconductor industry moves so slow, and proof-of-concept fabrication techniques take so long to productionize, that I doubt this is very far off.
The only thing marketing has done here is fight between each other on whether or not channel size is the number to focus on, as it benefits their corporation or not.
> These numbers refer to the length of the channel in the MOSFET or FinFET between the Source and Drain dopant regions. [...] The only thing marketing has done here is fight between each other on whether or not channel size is the number to focus on, as it benefits their corporation or not.
Right -- I believe this is where the variety (or marketing) creeps in.
Here's what I mean: The various "gate length" definitions (printed, physical, effective, etc.) have a direct (and significant) impact on the ambiguity of the meaning of "process nodes" (that's in addition to the half-pitch interpretation in the DRAM industry); cf. Table 1: ITRS 2013 Data for CMOS Technology “Nodes” in http://semiengineering.com/a-node-by-any-other-name/
For reference (for anyone else reading, I know you know this), "channel length" vs. "gate length" is another difference to take into account: http://vlsi-soc.blogspot.com/2015/12/channel-length-vs-gate-... (More formally -- "Sidebar: Gate Length (Lg) versus Channel Length (L) and Experimental Data versus Equations" in http://www-inst.eecs.berkeley.edu/~ee130/sp06/chp7full.pdf)
Given that, I think it's fair to say the result is that this is more of a marketing name than a directly (in terms of physical feature sizes) interpretable number; as in:
- "At the December meeting, for example, Chenming Hu, the coinventor of the FinFET, began by mapping out the near future. Soon, he said, we’ll start to see 14-nm and 16-nm chips emerge (the first, which are expected to come from Intel, are slated to go into production early next year). Then he added a caveat whose casual tone belied its startling implications: “Nobody knows anymore what 16 nm means or what 14 nm means.”"
- "The switch to FinFETs has made the situation even more complex. Bohr points out, for example, that Intel’s 22-nm chips, the current state of the art, have FinFET transistors with gates that are 35 nm long but fins that are just 8 nm wide."
http://spectrum.ieee.org/semiconductors/devices/the-status-o...
Related: http://spectrum.ieee.org/semiconductors/design/shrinking-pos...
That's certainly true for Google or Amazon but not for most real corporate IT departments. It's very common for small offices to need a local server for one reason or another even though the thing will be idle most of the time.
Moving the server into a larger datacenter would require a faster network link to that office which would be both more expensive and slower for local employees than the local server. So every little office gets a server which is mostly idle.
And then you need two of them for redundancy. And then you need four of them because one app touches credit cards and needs to be in the PCI CDE and the other doesn't etc. etc.
Compute cost matters when compute is a substantial part of your budget.
I can't speak for all corporate IT departments, but I'm at a very large corporation that certainly cares about idle power consumption. Over the years our servers have gotten more powerful, and more power hungry. It's not that hard to add more power, but adding new cooling isn't so easy. The less power we use overall, the less cooling we have to add, and the happier we are.
At this point, process nodes don't map to a particularly well-defined set of feature sizes across vendors. So what I assume they're saying is that what Intel calls 10nm is actually pretty similar in terms of transistor size/density to what TSMC is calling 7nm. (No idea if that's actually true but it's what I believe is being said.)
From a technology point of view the problem with EUV is more the line edge roughness, line width roughness, defects and the reliability... Given, more light will make the job easier
I think it's all but confirmed at this point that it's not progressing. What we're witnessing here is it's death.
If it's not dead, it's certainly dying. Perpetual exponential growth is irrational given finite resources.
I'm mostly speculating, though.
Secondary take away: due to the increased time to move to a better manufacturing process, Intel will likely not have as much a competitive advantage anymore. Though the number of competitors will (and has already) decrease due to the high investments.
Would be interesting to see how long intel estimates the process cycles are going to be, i.e. how Moore's law will progress.
Weird statement in the article: "it (TSCMs 7nm tech) should be very similar in terms of transistor density to Intel's 10-nanometer technology". This makes no sense as it would be comparing apples and pears. Surely they are referring to TSCMs 10nm tech?!