Why I will be using RISC-V in my next chip

Re:Why I will be using RISC-V in my next chip by wsxcde on Sunday January 10, 2016 @01:07AM (#10874416)

I suspect the DSP makers just use VLIW because of interia. They probably don't have the money or incentive to revisit their old decisions.

Also wouldn't you say that most of the stuff that used to be implemented on DSPs is now moving into ASICs? I wouldn't be so sure that VLIWs are going to be around forever.

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Re:Why I will be using RISC-V in my next chip by sklogic on Sunday January 10, 2016 @02:30AM (#10874571)

VLIW is many times cheaper (in terms of power and area) than OoO. It is not going anywhere from the low budget range.

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Re:Why I will be using RISC-V in my next chip by wsxcde on Sunday January 10, 2016 @12:53PM (#10876232)

But VLIW and OoO aren't the only two design points. The renewed interest in traditional inorder vector processors. In any case, I do think the point of DSPs was to be area/power efficient for certain specialized algorithms, and a lot of these are just becoming ASICs/specialized accelerators today.

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