PyComfy
Iconic yachts: On board Steve Jobs's Feadship superyacht Venus
https://www.boatinternational.com/yachts/editorial-features/...
Jobs died before it was finished.
import dis
dis.dis("a = foo.bar(b)")
1 0 LOAD_NAME 0 (foo)
2 LOAD_ATTR 1 (bar)
4 LOAD_NAME 2 (b)
6 CALL_FUNCTION 1
8 STORE_NAME 3 (a)
10 LOAD_CONST 0 (None)
12 RETURN_VALUE a = foo.bar(b)
ldict = locals()
ldict['a'] = ldict['foo'].__getattribute__('bar')(ldict['b'])[1] https://en.wikipedia.org/wiki/Gyrus
[2] https://en.wikipedia.org/wiki/Albert_Einstein%27s_brain#Newl...
https://blog.cloudflare.com/arm-takes-wing/
Multicore AVX512 lowers the frequency
The Qualcomm CPU only has the 128-bit wide NEON SIMD, while Broadwell has 256-bit wide AVX2, and Skylake has 512-bit wide AVX-512. This explains the huge lead Skylake has over both in single core performance. In the all-cores benchmark the Skylake lead lessens, because it has to lower the clock speed when executing AVX-512 workloads. When executing AVX-512 on all cores, the base frequency goes down to just 1.4GHz---keep that in mind if you are mixing AVX-512 and other code.
http://www.cs.vu.nl/~herbertb/download/papers/anc_ndss17.pdf
XI. CONCLUSIONS
In this paper, we described how ASLR is fundamentally insecure on modern architectures. Our attack relies on the interplay between the MMU and the caches during virtual to physical address translation—core hardware behavior that is central to efficient code execution on modern CPUs. The underlying problem is that the complex nature of modern microarchitectures allows attackers with knowledge of the architecture to craft a carefully chosen series of memory accesses which manifest timing differences that disclose what memory is accessed where and to infer all the bits that make up the address. Unfortunately, these timing differences are fundamental and reflect the way caches optimize accesses in the memory hierarchy. The conclusion is that such caching behavior and strong address space randomization are mutually exclusive. Because of the importance of the caching hierarchy for the overall system performance, all fixes are likely to be too costly to be practical. Moreover, even if mitigations are possible in hardware, such as separate cache for page tables, the problems may well resurface in software. We hence recommend ASLR to no longer be trusted as a first line of defense against memory error attacks and for future defenses not to rely on it as a pivotal building block.
Transpilation: text to text (eg: Scheme to C)
Compilation: anything to anything but usually it implies text to binary code
transpilation is compilation but compilation is not necessary transpilation (the all squares are rectangles but all rectangles ...)
https://web.archive.org/web/20120412091908/http://www.facult...
The popcnt example is nice.
before / after https://i.imgur.com/Ihy5wQh.png
https://scalibq.wordpress.com/2012/02/14/the-myth-of-cmt-clu...
http://www.anandtech.com/show/11170/the-amd-zen-and-ryzen-7-...
A lambda procedure is just an anonymous procedure.
A lambda is not necessary a closure and a closure is not necessary a lambda.