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A comment on Show HN: A pipelined RISC-V processor written in VHDL.

Re:Show HN: A pipelined RISC-V processor written in VHDL by nekoeth0 on Tuesday July 28, 2015 @05:50PM (#9964763)
Nice! I wrote a 5-stage pipelined RISC MIPS processor in SystemVerilog last semester, in one day, drunk as HELL, but hey, it worked amazingly well. Thank goodness they didn't ask for branch prediction.
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