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A comment on Designing a CPU in VHDL, Part 1: Rationale, Tools, Method. Parent comment

Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by rdc12 on Thursday June 18, 2015 @11:59PM (#9742945)
Just before the loop there is this instruction, "load.l r7, $mul16_fin".

Prehaps this is so the assembler/linker/loader doesn't need to resolve what address the label ends up having

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