News for hackers. Stuff that matters.

A comment on Designing a CPU in VHDL, Part 1: Rationale, Tools, Method.

Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by bobp127001 on Thursday June 18, 2015 @09:10PM (#9742554)
>bonus points goes to the people who realise there is an odd thing about the form of the baz (branch if Ra is zero) instruction.

Is this because the second argument is another register (presumably containing an address to branch to) instead of a label?

[ Parent | on HN ]
Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by rdc12 on Thursday June 18, 2015 @11:59PM (#9742945)
Just before the loop there is this instruction, "load.l r7, $mul16_fin".

Prehaps this is so the assembler/linker/loader doesn't need to resolve what address the label ends up having

[ Parent | on HN ]
Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by domipheus on Friday June 19, 2015 @04:21AM (#9743566)
yes! I've not implemented conditional jump to an immediate offset yet, so you need the branch target in a register.
[ Parent | on HN ]