Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by cyanoacry on Thursday June 18, 2015 @10:13PM (#9742690)

Having programmed in both, I prefer VHDL--the two take different paths, analogous to functional vs imperative programming.

The type checking that makes VHDL so annoying is also the same type checking that's saved me. Coming from Haskell, VHDL was a much easier language to learn than Verilog.

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Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by krupan on Friday June 19, 2015 @10:50AM (#9745128)

For those not familiar with these languages, saying that VHDL is functional programming and Verilog is imperative programming is misleading. Both use essentially the same style of modeling digital hardware (which is really neither of those): encapsulated modules with ports, clocked processes, and combinatorial logic.

Where they differ is mainly in typing. VHDL requires you (unlike haskell, actually) to (very verbosely) spell out the type of everything. Verilog's type system is more like C's. You declare basic types and it's fairly loosey goosey about them. VHDL's syntax is based on Ada and Verilog's is more C like (but uses begin-end instead of curly braces).

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