I don't have experience with Esterel in particular, but I can make some statements about imperative synchronous languages in general:

- They're a step in the right direction (e.g., implicit state machines), but then they're doing too much of a good thing. For example, in my experience, "abort" and especially "suspend" statements are not that important in non-toy examples, but they make the compiler more complex.

- Integrating external IP cores is difficult, but is absolutely essential for any real-world design.

- Even small FPGA designs contain usually at least two clock domains. This situation is typically impossible to design in imperative synchronous languages.

See Multiclock Esterel: http://link.springer.com/chapter/10.1007%2F3-540-44798-9_10

P.S.

Note that Esterel isn't mainly meant to design circuits but to write safety-critical hard realtime software.