Re:Why the Z-80's data pins are scrambled
by vidarh on Saturday September 27, 2014 @04:52AM
(#8376499)
The 6502 also has a similar 1-stage pipeline, and the concept was old already at that point, though not used much commercially outside of Cray's designs for CDC.
Re:Why the Z-80's data pins are scrambled
by reisgabrieljoao on Monday September 29, 2014 @11:32AM
(#8383354)
Essentially pipelining, several years before the RISC movement popularised it? Could the Z80 have been one of the first pipelined single-chip CPUs?
I don't think you can call it a pipeline, they only state that the different parts of the instruction are being decoded in parallel. For instance, which instruction will be executed and the register associated with the operation. There is no instruction pipeline.
Essentially pipelining, several years before the RISC movement popularised it? Could the Z80 have been one of the first pipelined single-chip CPUs?
That was a very interesting article. I've tried staring at the Visual6502 chip images for a long time, and although I understand the principles behind how diffusion/polysilicon/metal layers are put together to form transistors, for some reason I feel absolutely lost trying to follow the connections and find the borders between the regions especially when one layer is hidden beneath another.
Even looking at the NOR gate with its layout side-by-side I can't see much beyond the metal layer, despite it being partially transparent. I have no problems with transistor-level schematics, however. Is there some sort of trick to being able to easily read and follow the circuitry in die images and layout-level diagrams? It's like some people can read these and visualise/draw the schematic immediately.