reisgabrieljoao

Re:Why FPGA manufacturers keep their bitstream formats secret on Tuesday December 01, 2015 @11:42AM (#10656741)

>The ARM peripherals need to be assigned to I/O pins which happens in the FPGA (PL in Zynq terms).

ARM "hard" peripherals can be assigned to MIO pins, which have nothing to do with the PL, or EMIO which can be routed through PL to the FPGA pins. In both cases, the user must write to PS registers to configure internal muxes and assign the peripheral to a given set of pins. In the latter you must assign the ARM pin as an input in the PL and route it to a PL output as in any regular FPGA design.

>The ARM subsystem has bus connections to programmable logic which happens entirely in the FPGA (e.g., you connect a 16550 UART to the ARM via AXI bus, etc).

Yes it has but the interconnect subsystem is configured in software not through the bitsream.

> I'd say Zynq is a far more complex bitstream than just a vanilla FPGA.

Zynq's PL is a Xilinx 7 Series fabric, I wouldn't say both are much different in complexity. I'm not saying they're simple, tough...

Re:Why FPGA manufacturers keep their bitstream formats secret on Tuesday December 01, 2015 @08:21AM (#10655078)

The whole ARM subsystem configuration (at least in Zynq-7000) has nothing to do with the FPGA bitstream. It's all about configuring registers and can be done in software (normally by a bootloader) or through JTAG.

Re:On FPGAs as PC Coprocessors (1996) on Monday November 16, 2015 @12:54PM (#10575848)

There is a cache coherent FPGA-CPU DMA interface in Zynq-7000: the Accelerator Coherency Port (ACP).

Re:Analog's answer to FPGA opens field to masses (2008) on Tuesday November 11, 2014 @09:48AM (#8590017)

Rough estimates suggest there are around 3,000 analog engineers in the world

That's the real order of magnitude of the number of analog engineers?

Re:Why the Z-80's data pins are scrambled on Monday September 29, 2014 @11:32AM (#8383354)

Essentially pipelining, several years before the RISC movement popularised it? Could the Z80 have been one of the first pipelined single-chip CPUs?

I don't think you can call it a pipeline, they only state that the different parts of the instruction are being decoded in parallel. For instance, which instruction will be executed and the register associated with the operation. There is no instruction pipeline.