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Re:Say Hello to X64 Assembly Part 3 by pjmlp on Friday September 19, 2014 @06:29PM (#8342828)
In what regards modern processors I doubt very few humans are able to keep on their head, what each model and micro-code firmware release is doing to their micro-ops.
Re:Say Hello to X64 Assembly Part 3 by userbinator on Friday September 19, 2014 @08:59PM (#8343298)
That actually matters far less than most people think, because humans writing Asm do not (and should not) generate code like a compiler does.

The article has a great example of this in the int_to_str code. While it's far from optimal code (e.g. the "mov rbx, 10" should really be outside of the loop, the "add rdx, 0x0" is useless, etc.), it's using the stack in a way that a compiler would probably never do, and something that likely isn't possible to express at all in a HLL. The C version would involve at least allocating an array with some pointers into it to act as a stack.

It's in these approaches - fully exploiting the features of the machine - where human-written Asm really shines. In some ways, the compiler "has its hands tied" when it comes to generating code, since it is limited to generating code that represents ideas in the corresponding HLL; it can make use of extensive knowledge of microarchitecture to schedule instructions/uops, sophisticated algorithms for register allocation and instruction selection, and generate code that is faster on a particular model of CPU than if it did not, but this falls short of the human who realises that neither a separately allocated array, nor such instructions to manipulate it, are actually needed.

The human can apply even more extreme optimisation making use of microarchitectural details if she so chooses; but the fact is that even without this, the code is probably already better than what a compiler can do. In practice, for general-purpose-code (i.e. excluding additional features) most models of x86 are all quite similar since the P6, and Intel has been doing a great job at making existing code faster with each new generation, so there is little need to go to that extreme; the optimal sequence of instructions for one model is often the same or close to optimal for the next one. (The odd ones out are the P4, and possibly some of the early Atoms.)

Another item that appeared on HN a while ago illustrates this "think outside the HLL/compiler" idea too: http://davidad.github.io/blog/2014/02/25/overkilling-the-8-q... ( https://news.ycombinator.com/item?id=7301481 )

Re:Say Hello to X64 Assembly Part 3 by dllthomas on Friday September 19, 2014 @06:32PM (#8342846)
But sometimes you are faced with squeezing all the performance you can out of a specific processor.
Re:Say Hello to X64 Assembly Part 3 by pjmlp on Friday September 19, 2014 @06:47PM (#8342889)
And then comes a firmware update to the microcode...
Re:Say Hello to X64 Assembly Part 3 by dllthomas on Friday September 19, 2014 @06:52PM (#8342912)
And then you apply it in testing, note the regression, and either don't apply it in production or apply it as you push out an update.
Re:Say Hello to X64 Assembly Part 3 by pjmlp on Friday September 19, 2014 @07:38PM (#8343058)
Do you control all the processors your customers use?
Re:Say Hello to X64 Assembly Part 3 by dllthomas on Friday September 19, 2014 @07:48PM (#8343095)
If the software will be running on the machines of "customers" and you do not "control all the processors" they use, then you're not in the "sometimes" I was discussing above.
Re:Say Hello to X64 Assembly Part 3 by pjmlp on Saturday September 20, 2014 @01:05AM (#8343732)
That was what I was trying to say, somehow badly I guess.
Re:Say Hello to X64 Assembly Part 3 by dllthomas on Saturday September 20, 2014 @08:58AM (#8344389)
Yeah, I certainly didn't want to give the impression it was a common situation, just that it totally does happen.
Re:Say Hello to X64 Assembly Part 3 by floody-berry on Saturday September 20, 2014 @08:48AM (#8344369)
Do you have an example of this happening?