RISC-V: An Open Standard for SoCs

Re:RISC-V: An Open Standard for SoCs by renox on Tuesday August 12, 2014 @09:05AM (#8167551)

> All of the ISA's from the 70's and early 80's HAD an overflow feature.

All? The C was developed for the PDP11 which doesn't seem to have 'trap on overflow integer operations' like the MIPS has.

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Re:RISC-V: An Open Standard for SoCs by bsder on Thursday August 14, 2014 @07:55PM (#8180426)

Yeah, all. Or so close as to be indistinguishable from all.

If I'm really being pedantic, overflow detection was probably more prevalent than two's complement arithmetic at one point.

Directly from the PDP11 ISA:

BVC/BVS -- branch on overflow set/clear

Y'all need to go refresh your memory/study some history before arguing about this more. :)

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Re:RISC-V: An Open Standard for SoCs by renox on Monday August 18, 2014 @02:51AM (#8191650)

And you'd better read before replying: I said trap on integer overflow, not branch on integer overflow. The former gives you overflow check 'for free', the latter reduce the code density, which impact the instruction cache, which can reduce the performance. And in the early days, performance was above everything else, CPU being so slow..

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