> GPUs run at a pretty low clock rate anyway (600Mhz-1100Mhz), should be able to get 300-400Mhz out of an FPGA
An ASIC (GPUs are ASICs) running at 300 MHz can do a lot more per cycle than an FPGA at the same technology node running at the same frequency. A lot. Think order-of-magnitude more.
> The faulty logic elements / LUTs could just be marked as bad and not used.
This will screw up your timing, unless you reserve more setup slack (which in turn hurts the achievable performance).
I've got memories of a lab actually doing a wafer scale FPGA in the mid 90's. The reference escapes me, but if I can find it I'll post it. As you suggested, they preserved the yield by routing around defects.
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Edit: Or it might have been a PGA, rather than an FPGA.
There were some pushes for wafer scale stuff in the 80s [0], I think we are better suited from an algorithms, EDA and architecture standpoint now to actually make it work. A GPU is actually pretty good test bed and eventually GPU and FPGA functionality will merge into a single programmable compute fabric.
Yield on a wafer scale FPGA could actually be much better than a special purpose chip. The faulty logic elements / LUTs could just be marked as bad and not used.
[0] http://en.wikipedia.org/wiki/Wafer-scale_integration