This is a precursor to the next revolution in chips, 3D. It's funny how chips have of course always been three dimensional but the heat removal issues have so far stopped true 3D from happening (as far as I know). But SSDs have a completely different use pattern and likely don't run nearly as many Watts per volume of silicon so you could probably stack them way higher even if you didn't reduce the thickness of the layers all that much. Then it becomes a matter of routing and placement rather than heat dissipation.

Xilinx is already doing something like this: https://www.semiwiki.com/forum/showwiki.php?title=Semi+Wiki:...

Eventually this might even converge on something like a spherical shape, that's when the sum length of the connections is minimal (the surface area of the sphere is too, and that again is a heat removal problem).

Jim Gray was famous for predicting that the end point of computers were "smoking hairy golfballs". His reasoning was that spheres give you the shortest path length, there will be thousands of wires (hence the hair), and it will be difficult to dump the heat (smoking). I loved his image of a computer that looked like a a box of golf balls :-).

I read the paper you refer to, it in turn credits Frank Worrell as the original person coining that particular metaphor in ... 1985!

The paper quoted:

"To minimize memory latency these 4B machines will likely be smoking-hairy-golf-balls3. The processor will be one large chip wrapped in a memory package about the size of a golf ball. The surface of the golf ball will be hot and hairy: hot because of the heat dissipation, and hairy because the machine will need many wires to connect it to the outside world."

With a footnote:

"Frank Worrell used this metaphor in 1985."

The paper is here:

http://research.microsoft.com/en-us/um/people/gray/papers/su...

It's very interesting reading, especially when you look at how much he got right.

We don't quite have those smoking hairy golfballs just yet but we're slowly getting there.

That wasn't quite a prediction, it was the prevailing spirit of the times.

Ideally for volumes, yes, one would go for spheres. But in reality more often than not that translates to a cylinder because of technology trade-offs, with perhaps some endcaps. And not surprisingly, computing has already been there and done that.

If you take a bunch of compute nodes, roll the rack row up to minimize cable length, you end up with ...a classic Cray design from the '80s. And yes, the wiring in the middle of a cylindrical Cray was as 3D as it could physically get...

Looking at the picture, the technology of the era was an obvious dead-end:

https://upload.wikimedia.org/wikipedia/commons/f/f1/Cray-1-p...

and the trend is clear, just as it was back then with VLSI. Now the race is on to integrate those wires at a very large scale... (Cray also had a classic, visually appealing design approach to dump the heat, not unlike the enthusiast PC market today with commercial liquid coolers and some high-end HPCs)

Hehe, cool, that's a very close description of the mental image I had when I wrote that, I was afraid that it would be dissed as ridiculous.

I read that as "smoking hairy goofballs" and thought that perhaps he meant a bunch of weird old men with a cigar habit. Then you said spheres and it was all kinds of confusing.

I'd use RF from the controller to the different layers then you would only have to run power. Could even have 2 or 3 transmitters in phased array with little islands of storage on layers of silicon. This would also enable redundant storage (multiple recv) and simultaneous read and write (mimo). The distances in are cm and the signals wouldn't leave the drive package. With each layer exposing power and ground to the layer above the architecture would be scalable in Z just by adding more independent wafers.

https://eeweb.ee.ucla.edu/publications/journalVwaniRoychowdh...

http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.159...

Quite hard to do this reliably with 1000's of signals in a constricted space. It also requires considerably more circuitry than wiring would, the very first trick of routing is that you try to do your placement in such a way that the routing of signals is trivial. This is of course not always possible and it's a very complicated problem at chip scale but I don't see how adding 1000's of RF based signals would help here. You simply have to make sure that stuff stacked vertically lines up where you want the interconnects to be. After all, RF would not only require a lot of bandwidth, it would also right away require error correction and all kinds of transmission lines.

Optical would probably be even better than RF (and that too has its problems).

The wiring is localized and free since it is lithographed and short run. No long wires for transmission line effects and high power driving. Optical is option but I think harder socially and technically in the now-term.

60Ghz CMOS is already a thing http://www.seas.ucla.edu/brweb/papers/Journals/RJan06.pdf

http://www.home.agilent.com/upload/cmc_upload/All/Webinar_60...

Also http://en.wikipedia.org/wiki/Ultra-wideband

Watch out for the "Hazards of Prophecy"

Intel has been working on voxel, light-based vertical interconnects for nearly a decade.

I recall when I was there in '99 talking with people about stacking cores. Then a few years later some friends there were doing 64 core research in ~2003-4-ish...

I'm sure they have evolved the voxels since then.