This decade :)

For modern out-of-order CPUs - xor reg1,reg2 is problematic because the result depends on the previous contents of the register. Hence it cannot be executed out of order.

However as a special case xor reg1,reg1 (along with sub reg1,reg1) will be detected by the cpu (intel anyway) as a 'zero idiom' instruction and because it has a smaller opcode than mov reg,0 its preferred.

There are also other complex reasons - for detailed info see 3.5.1.8 in the Intel optimization manual.

>This decade :)

The initial claim was that mov reg,0 was slower to execute.

A CPU cycle is Fetch,Decode,Execute,Writeback. The 'zero idiom' instructions do not consume any 'Execute' resources. Apart from this.. as the other poster said, smaller opcodes means more instructions can fit inside the caches.

Smaller opcodes will, all else being equal, take up fewer instruction decide cycles and less space in the CPU cache.