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Re:Intel i7 loop performance anomaly by rayiner on Tuesday December 03, 2013 @10:54PM (#6844942)
I'm surprised that GCC generates that code. Using read-modify-write instructions directly in memory has been better on x86 processors for quite awhile now, since both AMD and Intel support fusing the memory and arithmetic operations into a single micro-op.
Re:Intel i7 loop performance anomaly by pbsd on Tuesday December 03, 2013 @11:30PM (#6845050)
Curiously enough, using separate reads and writes, with appropriate nop padding, seems to do better than any read-modify-write variation I tried.

By the way, read-modify-write is not fused altogether: only the write part is fused, so it generates 2 unfused uops (read, add), plus the fused uop for the write + address generation.

EDIT: Intel's compiler also generates read-modify-write code, but it ends up being slower than both gcc and clang.

Re:Intel i7 loop performance anomaly by nkurz on Wednesday December 04, 2013 @04:54PM (#6850567)
I also have gotten better results with separate read, modify, and write instructions than with combined. I think this is because the separate assembly statements allow for more explicit scheduling.
Re:Intel i7 loop performance anomaly by eliben on Tuesday December 03, 2013 @11:07PM (#6844986)
I was studying this difference between the two compilers for a different issue, actually. According to the standard, I don't see anything that prevents an increment of a volatile to be performed in a single instruction if the target permits it. Splitting it to a separate load+binop+store by gcc seems like an over-pessimization.