News for hackers. Stuff that matters.

A comment on Why Hardware Development Is Hard, Part 1: Verilog Is Weird. Parent comment

Re:Why Hardware Development Is Hard, Part 1: Verilog Is Weird by jck on Monday November 11, 2013 @06:07PM (#6714734)
oops, I guess that comment insinuates that I'm the creator of MyHDL. The creator of MyHDL is actually Jan Decaluwe(Sigasi, Easics). I just implemented the interfaces feature and develop uhdl.

Rgen looks really interesting. I hope you do manage to get it opensourced so that I can play with it!

[ Parent | on HN ]

There are no comments on this comment yet.