Why Hardware Development Is Hard, Part 1: Verilog Is Weird

Re:Why Hardware Development Is Hard, Part 1: Verilog Is Weird by ginty on Monday November 11, 2013 @08:43AM (#6711505)

Thanks for sharing, looks interesting.

Would you mind commenting on the development model for something like this? Do you do this on your own time or company sponsored time?

I mentioned in another comment that I have a framework along similar lines that has been developed within the company that I work for (Freescale Semiconductor) and I am looking for examples of other semiconductor-related open source projects that I can cite in discussions with management about releasing it.

If this was something that you developed within a company could you comment on how you went about open sourcing it?

[ Parent | on HN ]

Re:Why Hardware Development Is Hard, Part 1: Verilog Is Weird by jck on Monday November 11, 2013 @06:07PM (#6714734)

oops, I guess that comment insinuates that I'm the creator of MyHDL. The creator of MyHDL is actually Jan Decaluwe(Sigasi, Easics). I just implemented the interfaces feature and develop uhdl.

Rgen looks really interesting. I hope you do manage to get it opensourced so that I can play with it!

[ Parent | on HN ]