$30M Raised to Redo the CPU

Re:$30M Raised to Redo the CPU by 3reeDots on Wednesday November 11, 2026 @01:00AM (#50450162)

I think you are confusing CISC with specialized instructions. We just ask 3 questions to decide if something is CISC or RISC. 1. Are the instructions 32 bit wide? 2. Can the instruction only operate on registers? 3. Does it use microcoded, multi-cycle state machines for basic instructions?

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Re:$30M Raised to Redo the CPU by jcranmer on Wednesday November 11, 2026 @01:41AM (#50450364)

That's not the usual way to discuss CISC or RISC (and ARM fails two of the three questions anyways).

To be honest, CISC versus RISC has not been a useful distinction in architecture design for 30 years. Intel managing to make a superscalar CISC processor, the Pentium, should have put to bed any idea that there's a fundamental distinction between CISC and RISC that is useful.

The reality is that RISC isn't a single idea so much as it is a collection of ideas for how to design a microprocessor, and some of those ideas have turned out to be good and some of them have turned out to be bad. Rather than evaluating on the merits of RISC or CISC, we should evaluate on the merits of the embodied ideas. Let's stop trying to view 2020s design decisions based on 1970s models, okay?

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Re:$30M Raised to Redo the CPU by imtringued on Wednesday November 11, 2026 @08:43AM (#50453327)

I still don't really get why people are obsessed over RISC as an antagonist of CISC.

It's not like CISC or RISC are architectures like Transformers or Mamba. They're design philosophies with a huge amount of overlap and leeway.

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