That'd give you the best memory bandwidth. A single core is more than capable of saturating a single memory channel in certain streams of instructions.

Early AMD x86-64 chips were exactly that, and EPYC Naples (gen 1) was similar - each CCD had 2 memory channels. Later EPYCs ran the memory controllers from a separate IOD, in part because the strong NUMA topology was a bit too much for some OS's (Windows) to handle.

But these days with the very high core counts, it is infeasible for a memory channel per core.