Launch HN: Simantic (YC F26) – Firmware Simulation for AI Agents

Re:Launch HN: Simantic (YC F26) – Firmware Simulation for AI... by enough_ahnaf on Friday October 30, 2026 @04:21AM (#50301122)

Unfortunately yes, we are limited in the mixed signal domain right now, that is by design. you would need to interact with ICs at a data level or pin level transactions. This would be digital levels nothing analog.

This was kind of part of our original offerings to have a firmware mixed signal co-simulation. Run firmware--> see Spice level simulations happen. But this was a case where the speed to fidelity trade off really didnt make sense... yet. We were spreading ourselves thin on a long horizon project with nothing to show for it during the YC term.

We will come to revisit this problem for sure as we have heard many of our customers ask similiar question for analog IC purposes. Just have to take it one step at a time.

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Re:Launch HN: Simantic (YC F26) – Firmware Simulation for AI... by praveenrajus on Saturday October 31, 2026 @01:20PM (#50318052)

one spot where pin-level leaks is the ADC. tons of "firmware bugs" are really a big divider that can't recharge the sample cap in time, so readings come out low or depend on the previous channel. even just modeling source resistance vs sampling time would catch a lot of that

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