News for hackers. Stuff that matters.

A comment on VHDL's Crown Jewel. Parent comment

Re:VHDL's Crown Jewel by y1n0 on Monday March 30, 2026 @06:39AM (#47572620)
Reassigning clocks to another signal name will quickly get you into trouble in ways the just don’t happen on real hardware.
[ Parent | on HN ]
Re:VHDL's Crown Jewel by tverbeure on Monday March 30, 2026 @10:43AM (#47575014)
Have you heard about clock buffers and hold violations?
[ Parent | on HN ]
Re:VHDL's Crown Jewel by y1n0 on Tuesday March 31, 2026 @12:39AM (#47582815)
No, is that the latest craze?
[ Parent | on HN ]