Over the years I have run Altera, Lattice, and Xilinx... and almost all reasonably complex projects were always done in Verilog. If I recall Xilinx fully integrated its Synopsys export workflow a few years back, but not sure where that went after the mergers.

The Amaranth HDL python project does look fun =3

https://github.com/amaranth-lang/amaranth