Re:CERN uses tiny AI models burned into silicon for real-tim...
by tyjo99 on Monday March 30, 2026 @01:12PM
(#47577007)
I believe the way things are currently trending is that architectures might turn some short hard to predict branches into predicated instructions instead (similar to x86 CMOV or some ARM conditional execution instructions). Outside of short branches the overhead for loading up to 2 instructions for every 1 that gets executed can be too costly. Branch predication on SIMD/SIMT instructions is already the way things work for GPUs and AVX256/512 from my understanding.
I could see CPUs sometimes taking both paths for close, hard to predict branches. Does anyone have information on that?