RISC-V Is Sloooow

Re:RISC-V Is Sloooow by userbinator on Wednesday March 11, 2026 @12:08AM (#47331660)

I don't know if that construction might allow for a more efficient transistor count and it's totally impractical - 1KHz clock speed, 1-bit ALU, etc. - for almost any purpose, but it is technically a RISC-V implementation significantly smaller than 26K

That sounds like a microcoded RISC-V implementation, which can really be done for any ISA at the extreme expense of speed.

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Re:RISC-V Is Sloooow by inkyoto on Wednesday March 11, 2026 @01:28AM (#47331998)

If I'm not mistaken, microcode is a thing at least on Intel CPU's, and that is how they patched Spectre, Meltdown and other vulnerabilities – Intel released a microcode update that BIOS applies at the cold start and hot patches the CPU.

Maybe other CPU's have it as well, though I do not have enough information on that.

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