News for hackers. Stuff that matters.

A comment on RISC-V Is Sloooow. Parent comment

Re:RISC-V Is Sloooow by bobmcnamara on Tuesday March 10, 2026 @05:31PM (#47329049)
> The optimizations that'd be applied to ARM and MIPS would be equally applicable to RISC-V.

There's no carry bit, and no widening multiply(or MAC)

[ Parent | on HN ]
Re:RISC-V Is Sloooow by Findecanor on Tuesday March 10, 2026 @08:09PM (#47330377)
RISC-V splits widening multiply out into two instructions: one for the high bits and one for the low. Just like 64-bit ARM does.

Integer MAC is hindered by a design decision not to require more than two source operands, so as to allow simple implementations to stay simple. FMAC exists, but only because it is in the IEEE 754 spec ... and it requires significant op-code space.

[ Parent | on HN ]