The Hardware Renaissance

Re:The Hardware Renaissance by jgw on Tuesday October 23, 2012 @04:24PM (#4690170)

There are a number of solutions that do that kind of thing to a degree - and they are improving. For certain types of designs, you can actually compile fairly unrestricted C and C++ into gates that are faster and lower gate-count than hand-coded Verilog designs. Your friend's domain might well be one of them.

I think you need some specialized knowledge to use this existing generation of tools, but having never used such tools, I couldn't quantify that.

I'm also not sure how well these tools perform on arbitrary hardware designs.

But no - I certainly don't think he's out to lunch.

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Re:The Hardware Renaissance by btilly on Tuesday October 23, 2012 @05:47PM (#4690510)

The problem is that C and C++ do not implicitly parallelize well. To get maximum bang for the bunk you want to extract lots of parallelism. Which requires a different kind of language.

The interesting flip side is that if you design for easy parallelism, you are better able to take advantage of multiple cores in standard CPUs. Also you can then turn it around and also distribute the same program across a cluster of commodity hardware on the cloud.

But yes, the toolchain matters. A lot.

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Re:The Hardware Renaissance by ableal on Tuesday October 23, 2012 @06:01PM (#4690574)

> maximum bang for the bunk

That ranks up with "rear-window defrogger" and "string-loaded door" in my collection of amusing typos ...

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Re:The Hardware Renaissance by btilly on Tuesday October 23, 2012 @09:03PM (#4691154)

Oops.

I will have to look for an opportunity to use it on purpose.

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