The Hardware Renaissance

Re:The Hardware Renaissance by btilly on Tuesday October 23, 2012 @04:08PM (#4690100)

I have a friend who has been trying to convince me that it is feasible to create a language that can let a general purpose programmer write useful software and "compile" it down to a FPGA to run really, really fast. (He has a lot of specific thoughts that I won't share about what such a language should look like.)

In principle he thinks that it should be possible to compile such a language down to an ASIC representation, but that would only make sense for very high volume runs. (He's specifically interested in software to run financial models, so those would not be high volume runs.)

He makes sense to me, but I have no idea what practical difficulties there would be. But does something like this sound doable in principle from your point of view?

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Re:The Hardware Renaissance by jgw on Tuesday October 23, 2012 @04:24PM (#4690170)

There are a number of solutions that do that kind of thing to a degree - and they are improving. For certain types of designs, you can actually compile fairly unrestricted C and C++ into gates that are faster and lower gate-count than hand-coded Verilog designs. Your friend's domain might well be one of them.

I think you need some specialized knowledge to use this existing generation of tools, but having never used such tools, I couldn't quantify that.

I'm also not sure how well these tools perform on arbitrary hardware designs.

But no - I certainly don't think he's out to lunch.

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Re:The Hardware Renaissance by btilly on Tuesday October 23, 2012 @05:47PM (#4690510)

The problem is that C and C++ do not implicitly parallelize well. To get maximum bang for the bunk you want to extract lots of parallelism. Which requires a different kind of language.

The interesting flip side is that if you design for easy parallelism, you are better able to take advantage of multiple cores in standard CPUs. Also you can then turn it around and also distribute the same program across a cluster of commodity hardware on the cloud.

But yes, the toolchain matters. A lot.

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Re:The Hardware Renaissance by ableal on Tuesday October 23, 2012 @06:01PM (#4690574)

> maximum bang for the bunk

That ranks up with "rear-window defrogger" and "string-loaded door" in my collection of amusing typos ...

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Re:The Hardware Renaissance by btilly on Tuesday October 23, 2012 @09:03PM (#4691154)

Oops.

I will have to look for an opportunity to use it on purpose.

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Re:The Hardware Renaissance by Peaker on Tuesday October 23, 2012 @07:01PM (#4690798)

Bluespec is trying to do something similar to this, but they focus on synthesizing hardware, software is a secondary thing. However, it's designed to run well in software too.

Originally implemented by one of the major Haskell gurus, Augustusson.

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Re:The Hardware Renaissance by sterna on Wednesday October 24, 2012 @09:36AM (#4692855)

You can already do this with Labview and National Instruments hardware. It is quite easy to program and Labview is inherently a parallel language so you get that for free, but the price is way too high.

One FPGA module costs around 3000 $ and a Labview licence costs around 10000 $, at least in Denmark. It is probably cheaper in the US.

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Re:The Hardware Renaissance by fieldforceapp on Tuesday October 23, 2012 @04:40PM (#4690242)

Commercial EDA vendors have solutions starting from C, Matlab and LISA for synthesis of HW logic into FPGA or ASICs. One such list of products is here:

http://www.synopsys.com/Systems/BlockDesign/Pages/default.as...

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Re:The Hardware Renaissance by seltzered_ on Tuesday October 23, 2012 @06:00PM (#4690573)

dataflow languages like labview already market this, no idea how performant it is though.

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