Or you could do the right thing, ignore the GUI for 99% of what you’re doing, and treat the FPGA tools as command line tools that are invoked by running “make”…

This is how most FPGA users interact with vivado/quartus these days.

One really wonders when reading some of the comments here…

I should have said "most _professional_ FPGA users" because I assume many people here who don't know this (including the author of the article) are not.

Any good guides you'd recommend to get started? Also does this workflow work with the cheap Chinese FPGAs available on aliexpress (tang nano, etc)? I always wanted to try out FPGAs again and I prefer to work from command line when possible.

You can pretty much do everything in Vivado from the command line as long as you know Tcl...

Also, modern Verilog (AKA Systemverilog) fixes a bunch of the issues you might have had. There isn't much advantage to VHDL these days unless perhaps you are in Europe or work in certain US defense companies.

# Here's the general flow for Vivado TCL projects that takes you from source code to a bit-file with no interaction. Read UG835 for details.

create_project -in_memory -part ${PART}

set_property target_language VHDL [ current_project ]

read_vhdl "my_hdl_file.vhd"

synth_design -top my_hdl_top_module_name -part ${PART}

opt_design

place_design

route_design

check_timing -file my_timing.txt

report_utilization -file my_util.txt

write_checkpoint my_routed_design.dcp

write_bitstream my_bitfile.bit

The main advantage to VHDL is the style of thinking it enforces. If you write your Verilog or SystemVerilog like it's VHDL, everything works great. If you write your VHDL like it's Verilog, you'll get piles of synthesis errors... and many of them will be real problems.

So if you learn VHDL first, you'll be on a solid footing.

I think this can just be summarized to "write any HDL like you are modeling real hardware." Both VHDL and Systemverilog were primarily intended for validation and synthesis is a second class citizen.

There is a trend among programmers to assume that everything supported by the syntax can be done. This is not even true in C++, but it's something people think. If you are writing synthesizable SystemVerilog, only a small subset of the language used in a particular set of ways works. You have to resist the urge to get too clever (in some ways, but in other ways you can get extremely clever with it).

I thought that if you have some idea about how hardware works, it is kind of more or less obvious whether something is synthesizable or not.

I haven't learned Verilog, only VHDL and even that with the explicit <register>_ff <= <register_nxt> pattern when I need flips flops and I never felt like there is anything difficult about VHDL

Is the North American insistence on teaching Verilog what's setting up students for failure since Verilog looks a bit more like a sequential programming language at first glance?

VHDL is based on Ada, so it also inherits from sequential programming models.

Well really, the language _is_ the difficulty of much of hardware design, both Verilog and VHDL are languages that were designed for simulation of hardware, and not synthesis of hardware. Both languages have of similar-but-not-quite ways of writing things, like blocking/nonblocking assigns causing incorrect behavior that's incredibly difficult to spot on the waveform, not being exhaustive in assigns in always blocks causing latches, maybe-synthesizeable for loops, etc. Most of this comes from their paradigm of an event loop, handling all events and the events that those events trigger, etc, until all are done, and advancing time until the next event. They simulate how the internal state of a chip changes every clock cycle, but not to actually do the designing of said chip itself.

I'm tooting my own horn with this, as I'm building my own language for doing the actual designing. It's called SUS.

Simple things look pretty much like C:

  module add :
    int#(FROM:-8, TO: 8) a,
    int#(FROM: 2, TO: 20) b -> 
    int c {
    c = a+b
  }

It automatically compensates for pipelining registers you add, and allows you to use this pipelining information in the type system.

It's a very young language, but me, a few of my colleagues, and some researchers in another university are already using it. Check it out => https://github.com/pc2/sus-compiler

VHDL was designed for specification. Verilog is the one with the warts from its simulator heritage.

Language really isn't the difficulty. That's why there's a thousand alt-HDLs that have been used for little more than blinking LEDs.