Re:Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes
by achr2 on Friday November 28, 2025 @02:30PM
(#46081969)
>> Even if it only catches one small, it could save thousand of dollars down the line.
Or it could send a design team down thousands of dollars in false positives/false negatives. With zero benchmarks provided, it is very fair to question a product that could have material negative impacts on a hardware team.
Re:Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes
by proee on Friday November 28, 2025 @02:36PM
(#46082015)
The tool would ideally classify the output into levels. Just like a compiler or DRC checker. If you submit a clean design, the tool should not be throwing major flags. 99% of the time you should be getting advisory outputs, which should not be tricking any designer. The 1% red flags should easily be understood and if you, as the designer, can't discern them, perhaps you don't understand the fundamentals of your own design.
Re:Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes
by unmole on Saturday November 29, 2025 @12:24AM
(#46085355)
> tone of your reply is a skeptical engineer with arms crosses.
So, just a typical HN comment?
Re:Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes
by tomhow on Saturday November 29, 2025 @04:22PM
(#46090901)
Please don't sneer, including at the rest of the community. - https://news.ycombinator.com/newsguidelines.html
Comments in Show HN threads are generally curious and supportive. Yes, there are notable exceptions.
We detached this comment from https://news.ycombinator.com/item?id=46081918 and marked it off topic.
I see this idea as a sort of AI ERC/DRC checker that offers some incredible opportunities. Even if it only catches one small, it could save thousand of dollars down the line.
It's another tool in the toolbox for hardware designers.