Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove...
by BobbyTables2 on Monday September 08, 2025 @10:07PM
(#45176583)
I vaguely thought it was to provide another source of potentially “ready” instructions when the main thread was blocked on I/O to main memory (such as when register renaming can’t proceed because of dependencies).
But I could be way off…