Condor's Cuzco RISC-V Core at Hot Chips 2025

Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by 0x000xca0xfe on Saturday August 30, 2025 @11:43AM (#45075590)

It's just shorthand for "level 2 cache", "level 3 cache", "instruction cache" and "data cache".

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Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by daneel_w on Saturday August 30, 2025 @12:21PM (#45075847)

Yes, obviously. It's just the first time I've seen a CPU designer/manufacturer use such relaxed "informality" in a spec sheet.

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Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by Findecanor on Saturday August 30, 2025 @01:58PM (#45076706)

I follow RISC-V and see it all the time.

CPU manufacturers also aren't using Unicode, using the letter u instead of µ (micro), and the letter A instead of Å (the unit Ångström).

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Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by DiabloD3 on Saturday August 30, 2025 @01:19PM (#45076361)

I've been seeing it more and more, especially with vendors that don't speak a western language on their spec sheets.

Everyone can tell what L1$ means, but what would L1 缓存 mean?

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Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by jasonwatkinspdx on Saturday August 30, 2025 @10:51PM (#45079925)

The slides are for Hot Chips, which is a very engineering focused venue. It's not your normal marketing stuff.

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Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by Brian_K_White on Wednesday September 03, 2025 @12:15AM (#45112209)

I got it, and hate it.

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