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Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by daneel_w on Saturday August 30, 2025 @11:22AM (#45075405)
"L2$, L3$, I$, D$". Well, OK.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by 0x000xca0xfe on Saturday August 30, 2025 @11:43AM (#45075590)
It's just shorthand for "level 2 cache", "level 3 cache", "instruction cache" and "data cache".
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by daneel_w on Saturday August 30, 2025 @12:21PM (#45075847)
Yes, obviously. It's just the first time I've seen a CPU designer/manufacturer use such relaxed "informality" in a spec sheet.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by Findecanor on Saturday August 30, 2025 @01:58PM (#45076706)
I follow RISC-V and see it all the time.

CPU manufacturers also aren't using Unicode, using the letter u instead of µ (micro), and the letter A instead of Å (the unit Ångström).

Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by DiabloD3 on Saturday August 30, 2025 @01:19PM (#45076361)
I've been seeing it more and more, especially with vendors that don't speak a western language on their spec sheets.

Everyone can tell what L1$ means, but what would L1 缓存 mean?

Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by jasonwatkinspdx on Saturday August 30, 2025 @10:51PM (#45079925)
The slides are for Hot Chips, which is a very engineering focused venue. It's not your normal marketing stuff.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by Brian_K_White on Wednesday September 03, 2025 @12:15AM (#45112209)
I got it, and hate it.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by bee_rider on Saturday August 30, 2025 @11:24AM (#45075423)
Hmm?
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by daneel_w on Saturday August 30, 2025 @12:38PM (#45075965)
Cache is pronounced like cash, which the $ symbol is supposed to allude to.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by xxpor on Saturday August 30, 2025 @03:42PM (#45077433)
Wow, how have I never put 2 and 2 together on that.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by robinsonb5 on Saturday August 30, 2025 @05:23PM (#45078132)
You're not alone - it took me way longer than it should have done to figure that one out!
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by bee_rider on Saturday August 30, 2025 @12:50PM (#45076054)
Yes, they are obviously caches. I just didn’t understand your comment.
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by starkruzr on Saturday August 30, 2025 @05:43PM (#45078249)
leading to the unfortunate abbreviation sometimes drawn on blackboards, "$hit"
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by grg0 on Saturday August 30, 2025 @10:01PM (#45079661)
It is an apt abbreviation if you visualize shit tightly packed in a container. And when you thrash the cache, shit hit the fan (and spills to VRAM.)
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by bitwize on Saturday August 30, 2025 @12:22PM (#45075855)
Ooh, I wonder what strings were put in those BASIC variables...
Re:Condor's Cuzco RISC-V Core at Hot Chips 2025 by daneel_w on Saturday August 30, 2025 @12:25PM (#45075873)
LET L2$="256 KiB"; LET L3$="8 MiB"