Re:Ask HN: Why hasn't x86 caught up with Apple M series?
by DanielHB on Tuesday August 26, 2025 @09:18AM
(#45026131)
I don't think it is so much efficiency of their chips for their hardware (phones) so much as efficiency of their OS for their chips and hardware design (like unified memory).
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Re:Ask HN: Why hasn't x86 caught up with Apple M series?
by zipityzi on Tuesday August 26, 2025 @09:34AM
(#45026335)
It is likely the hardware effiency of their chips. Apple SoCs running industry-standard benchmarks still run very cool, yet still show dominant performance. The OS efficiency helps, but even under extreme stress tests like SPEC, the Apple SoCs dominate in perf & power.
See Lunar Lake on TSMC N3B, 4+4, on-package DRAM versus the M3 on TSMC N3B, 4+4, on-package DRAM: https://youtu.be/ymoiWv9BF7Q?t=531
The 258V (TSMC N3B) has a worse perf / W 1T curve than the Apple M1 (TSMC N5).
Re:Ask HN: Why hasn't x86 caught up with Apple M series?
by jhoechtl on Tuesday August 26, 2025 @11:40AM
(#45028075)
> It is likely the hardware effiency of their chips. Apple SoCs running industry-standard benchmarks still run very cool, yet still show dominant performance
Dieselgate?
Re:Ask HN: Why hasn't x86 caught up with Apple M series?
by Eric_WVGG on Tuesday August 26, 2025 @11:06AM
(#45027632)
I have heard that Apple Silicon chips are designed around the retain-release cycle that goes back to NeXT and is still here today (hidden by ARC compilation), but I don't think that's the whole story. Back when the M1's came out, many benchmarks showed virtualized Windows blowing the doors off of market-equivalent x86 CPUs.
Also, there's the obvious benefits of being TSMC's best customer. And when you design a chip for low power consumption, that means you've got a higher ceiling when you introduce cooling.
Re:Ask HN: Why hasn't x86 caught up with Apple M series?
by waffletower on Tuesday August 26, 2025 @11:38AM
(#45028045)
The SoC benefits are being ignored by some people here. Apple doesn't control every piece of software as some here posit, however, OS optimizations and utilization of extra-efficiency cores (though still requiring SoC design they do also need specific OS code support) are part of the performance.