Show HN: I built a toy TPU that can do inference and training on the XOR problem

Re:Show HN: I built a toy TPU that can do inference and trai... by skybrian on Monday August 18, 2025 @05:44PM (#44945671)

It's unclear to me what the end result is. Did you build real hardware or is it simulated somehow? If it's hardware, what kind and how did you make it?

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Re:Show HN: I built a toy TPU that can do inference and trai... by jacquesm on Monday August 18, 2025 @05:54PM (#44945736)

Verilog spec by the looks of it. So you should be able to make it work on an FPGA or if you happen to have a chip fab in your garage you might want to make your own silicon ;) I'd go the FPGA route.

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Re:Show HN: I built a toy TPU that can do inference and trai... by antognini on Monday August 18, 2025 @05:54PM (#44945733)

Based on the code in the repo it looks like they designed the chip in verilog and then ran it in a simulator. But if they have the verilog code in principle they could send it off to a fab and get real hardware back.

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Re:Show HN: I built a toy TPU that can do inference and trai... by UncleOxidant on Monday August 18, 2025 @07:51PM (#44946664)

Next step would be to try it out in an FPGA.

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Re:Show HN: I built a toy TPU that can do inference and trai... by zhainya on Monday August 18, 2025 @06:04PM (#44945801)

I feel like I missed a whole section somewhere. "Built a toy TPU". What does that mean? I have no idea what was actually "built" here.

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Re:Show HN: I built a toy TPU that can do inference and trai... by evxxan on Monday August 18, 2025 @06:54PM (#44946181)

By "toy TPU", we simulated forward pass + backprop on a minimal tpu-like accelerator.

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Re:Show HN: I built a toy TPU that can do inference and trai... by evxxan on Monday August 18, 2025 @06:52PM (#44946163)

all in simulation :)

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