While Amaranth is notably Python-for-hardware, I think the real standout feature is that it all but eliminates the infamous simulation-vs-synthesis mismatch. Verilog can simulate perfectly yet explode in synthesis, but Amaranth omits non-synthesizable constructs and enforces explicit instantiation. The result: a design that passes simulation is far more likely to synthesize identically, averting costly back-end surprises. If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas, that philosophy alone makes Amaranth worth a look.