Re:Public Domain FPGA Architecture
by al2o3cr on Monday August 04, 2025 @11:39AM
(#44787346)
I don't understand what one long line of Verilog in a repo is supposed to demonstrate.
Also, your "solution" of the halting problem amounts to "run the program and see if it halts", which ISN'T A SOLUTION. A machine that for each step puts a 1 on the tape and moves right, repeat forever, would never "match the current savestate".
Also, your "solution" of the halting problem amounts to "run the program and see if it halts", which ISN'T A SOLUTION. A machine that for each step puts a 1 on the tape and moves right, repeat forever, would never "match the current savestate".