Re:Cache Lines Are The New Registers
by stephencanon on Sunday September 02, 2012 @01:25PM
(#4467548)
Yes, modern out-of-order processors have on the order of 200 physical registers which are mapped to program registers by renaming.
Cache and register utilization are critical (register utilization not so much because of the latency of loads from cache--which are fast--as because loads from cache are a scarce resource; a typical core can manage only one or two per cycle), but maximizing TLB reach turns out to be even more important than cache for some algorithms that deal with large data sets.
Cache and register utilization are critical (register utilization not so much because of the latency of loads from cache--which are fast--as because loads from cache are a scarce resource; a typical core can manage only one or two per cycle), but maximizing TLB reach turns out to be even more important than cache for some algorithms that deal with large data sets.