Cache Lines Are The New Registers

Re:Cache Lines Are The New Registers by Lagged2Death on Sunday September 02, 2012 @01:18PM (#4467519)

Don't modern CPUs (like x86) have about a zillion registers internally, which are, behind the scenes, allocated to the virtual registers (AX, BX, CX etc) that are seen from the assembly level?

Itanium has a register stack, and I'm pretty sure it wasn't the first.

http://software.intel.com/en-us/articles/itaniumr-processor-...

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Re:Cache Lines Are The New Registers by stephencanon on Sunday September 02, 2012 @01:25PM (#4467548)

Yes, modern out-of-order processors have on the order of 200 physical registers which are mapped to program registers by renaming.

Cache and register utilization are critical (register utilization not so much because of the latency of loads from cache--which are fast--as because loads from cache are a scarce resource; a typical core can manage only one or two per cycle), but maximizing TLB reach turns out to be even more important than cache for some algorithms that deal with large data sets.

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