Normally fp numbers have an "invisible leading one bit", so an ieee fp is (1+0.nnnn) x 2^E where nnn is the mantissa and E is the exponent.

as posits are always two's complement, you can model negative posits as having an "invisible leading two bit", aka (2-0.nnnn) x 2^E-1. this greatly simplifies circuitry for addition and multiplication.

> the addition operation takes up quite a bit more floorspace,

I miswrote, it's multiplication. This is simple: since the math requires floorspace of size n^2 where n is the maximum resolution of the mantissa, and posits have more resolution around unity.

we did floorspace estimates for fp32 versus p32 and it looked like the extra space required for the mantissa did not overtake the savings from the crazy logic required for sign flipping, nans, and denormals that IEEE requires that posits don't.

> I was hoping the current AI hype wave would bring some custom silicon for alternative float formats, Posits included

i was hoping for this too!