Normally fp numbers have an "invisible leading one bit", so an ieee fp is (1+0.nnnn) x 2^E where nnn is the mantissa and E is the exponent.
as posits are always two's complement, you can model negative posits as having an "invisible leading two bit", aka (2-0.nnnn) x 2^E-1. this greatly simplifies circuitry for addition and multiplication.
> the addition operation takes up quite a bit more floorspace,
I miswrote, it's multiplication. This is simple: since the math requires floorspace of size n^2 where n is the maximum resolution of the mantissa, and posits have more resolution around unity.
we did floorspace estimates for fp32 versus p32 and it looked like the extra space required for the mantissa did not overtake the savings from the crazy logic required for sign flipping, nans, and denormals that IEEE requires that posits don't.
> I was hoping the current AI hype wave would bring some custom silicon for alternative float formats, Posits included
i was hoping for this too!
There's a tentative standard btw: https://posithub.org/docs/posit_standard-2.pdf
Ahh indeed! I'm working on a software posit implementation (for fun, I'll eventually post it as a rust crate) so I already make use of this trick :) decoding a p64 into an exponent and twos complement signed mantissa can be done in 9 instructions on x86!
Curious, what trick? :)
Wishing for mainstream CPU support for anything but IEEE numbers was always a pipe dream on anything but the decades-long term, but I gotta be honest, I was hoping the current AI hype wave would bring some custom silicon for alternative float formats, Posits included.
> the addition operation takes up quite a bit more floorspace, and just quantizing to int4 is with grouped scaling factors is easier with existing gpu pipelines
Can you elaborate on this part?