- SMIC's Ascend 910B has a die size of 665.61mm², which is more than 6x larger.
- The AI chiplet of Ascend 910 itself is already significantly larger than the whole Kirin 9000s die. There's no data on it from SMIC, but when TSMC produced it with equivalent N7+ process, it was 456.25mm² (>4x larger)
I don't know about the rumored 20% yield, but this difference in die-size alone would dramatically impact yield for the Ascend design. And that's just ONE factor.
SMIC could have achieved a 90% yield with Kirin 9000s and still be at 20% with Ascend 910...
Anyway. Since the company doesn't publish these numbers everything is secondary sources and dominated (at least in the English language media) by politics.
What you can do is look at objective indicators such as what gets sold (phones, computers) where (China, outside China). And prices and availability of Chinese cloud computing and AI products.
A big thing would be for the Huawei 910C to show up outside China.
Yes.
As written, the (Virtuvian) AI processor CHIPLET of Ascend 910 with TSMC N7+ process has a size of 456.25mm², >4x larger than the whole Kirin SoC.
Rumor is that 910C was aimed to not redesign them significantly compared to the 910B iteration but double the amount of those AI chiplets in one package.
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> What you can do is look at objective indicators such as what gets sold (phones, computers) where (China, outside China). And prices and availability of Chinese cloud computing and AI products.
The size of the chiplet in the comparable TSMC N7+ process is objectively known, the size of the Kirin 9000s SoC die is objectively known.
Those are good indicators that the commercial volume of the mass-produced die (Kirin) doesn't tell you much about the potential yield for the 4x larger AI-chiplet (Ascend 910 Virtuvian)
We have no idea if the chips are just being heavily subsidized to deal with the low yields. If it isn’t free market, the prices they offer aren’t going to tell us much, and if it subsidized heavily it won’t be very sustainable.