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A comment on A FPGA friendly 32 bit RISC-V CPU implementation. Parent comment

Re:A FPGA friendly 32 bit RISC-V CPU implementation by bri3d on Saturday January 25, 2025 @11:13PM (#42827651)
Thank you for the correction! My original comment is too old to update. It’s so frequently described as one (for example in https://github.com/SpinalHDL/SpinalHDL/issues/202#issuecomme... ) that I assumed they shared a history.
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