Re:A FPGA friendly 32 bit RISC-V CPU implementation
by fayalalebrun on Saturday January 25, 2025 @09:37PM
(#42827206)
SpinalHDL did not fork from Chisel. You might be able to say that it was inspired by Chisel, but it does not share a commit history. See this comment by the author: https://www.reddit.com/r/chisel/comments/4ivevd/comment/d3lj...
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Re:A FPGA friendly 32 bit RISC-V CPU implementation
by bri3d on Saturday January 25, 2025 @11:13PM
(#42827651)
Thank you for the correction! My original comment is too old to update. It’s so frequently described as one (for example in https://github.com/SpinalHDL/SpinalHDL/issues/202#issuecomme... ) that I assumed they shared a history.