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A comment on A FPGA friendly 32 bit RISC-V CPU implementation. Parent comment

Re:A FPGA friendly 32 bit RISC-V CPU implementation by wespiard on Saturday January 25, 2025 @04:06PM (#42824854)
I don't know much about SpinalHDL or Chisel, but one example of an alternate HDL is HardCaml, which is used by JaneStreet for FPGA designs:

https://github.com/janestreet/hardcaml

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