Re:Gate-level simulation of ASIC in browser
by tmvphil on Wednesday January 08, 2025 @02:45PM
(#42637745)
Completely wild to me that you are backing out the netlist from the geometry gds.
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Re:Gate-level simulation of ASIC in browser
by znah on Wednesday January 08, 2025 @02:50PM
(#42637788)
First I implemented it, and then learned that it is called Layout vs Schematic (LVS). For now automatic conversion is limited to stateless cells, but I'm planning to rewrite the circuit extractor to support all flipflops and latches.