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A comment on Intel Announces Retirement of CEO Pat Gelsinger. Parent comment

Re:Intel Announces Retirement of CEO Pat Gelsinger by alganet on Monday December 02, 2024 @01:22PM (#42298815)
> One of the key reasons why Rosetta 2 provides such a high level of translation efficiency is the support of x86-64 memory ordering in the Apple M1 SOC.

https://www.sciencedirect.com/science/article/pii/S138376212...

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Re:Intel Announces Retirement of CEO Pat Gelsinger by ryao on Monday December 02, 2024 @04:00PM (#42300329)
TSO might be slower than ARM’s memory ordering, but implementing it in hardware is considered faster than implementing it in software.
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