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A comment on DRAM Changed the World. Parent comment

Re:DRAM Changed the World by rasz on Thursday October 24, 2024 @12:45AM (#41931988)
Yep, we pretty much hit a wall during DDR2 rein https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_exam...
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Re:DRAM Changed the World by anticensor on Friday October 25, 2024 @10:25PM (#41952016)
No, 7.5 to 9.75ns during the DDR4 rein (DDR4-4266), according to that page.
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Re:DRAM Changed the World by rasz on Saturday October 26, 2024 @02:31AM (#41952978)
DDR2-1066 CL4 is also 7.5ns to first data.
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Re:DRAM Changed the World by anticensor on Saturday October 26, 2024 @05:56AM (#41953757)
But DDR2-1066 is worse in second and later accesses.
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Re:DRAM Changed the World by rasz on Sunday October 27, 2024 @06:22PM (#41966164)
Consequent accesses are measuring bus speed, not actual DRAM cell latency. At that point data is already loaded into a row of sense amplifiers.
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